Alif Semiconductor /AE722F80F55D5LS_CM55_HP_View /ETH /ETH_MTL_TXQ0_DEBUG

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Interpret as ETH_MTL_TXQ0_DEBUG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0x0)TXQPAUSED 0 (Val_0x0)TRCSTS 0 (Val_0x0)TWCSTS 0 (Val_0x0)TXQSTS 0 (Val_0x0)TXSTSFSTS 0PTXQ0STXSTSF

TXSTSFSTS=Val_0x0, TWCSTS=Val_0x0, TRCSTS=Val_0x0, TXQSTS=Val_0x0, TXQPAUSED=Val_0x0

Description

Queue 0 Transmit Debug Register

Fields

TXQPAUSED

Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: Reception of the PFC packet for the priorities assigned to the Tx Queue when PFC is enabled Reception of 802.3x Pause packet when PFC is disabled

0 (Val_0x0): Transmit queue in pause status is not detected

1 (Val_0x1): Transmit queue in pause status is detected

TRCSTS

MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:

0 (Val_0x0): Idle state

1 (Val_0x1): Read state (transferring data to the MAC transmitter)

2 (Val_0x2): Waiting for pending Tx status from the MAC transmitter

3 (Val_0x3): Flushing the Tx Queue because of the packet abort request from the MAC

TWCSTS

MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx Queue Write Controller is active, and it is transferring the data to the Tx Queue.

0 (Val_0x0): MTL Tx Queue write controller status is not detected

1 (Val_0x1): MTL Tx Queue write controller status is detected

TXQSTS

MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue is not empty and some data is left for transmission.

0 (Val_0x0): MTL Tx Queue not empty status is not detected

1 (Val_0x1): MTL Tx Queue not empty status is detected

TXSTSFSTS

MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. Therefore, the MTL cannot accept any more packets for transmission.

0 (Val_0x0): MTL Tx Status FIFO full status is not detected

1 (Val_0x1): MTL Tx Status FIFO full status is detected

PTXQ

Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set to 1, this field does not reflect the number of packets in the Transmit queue.

STXSTSF

Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the ETH_MTL_OPERATION_MODE[DTXSTS] bit is set to 1, this field does not reflect the number of status words in Tx Status FIFO.

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